This invention is directed to inverter circuits and, in particular, to thyristor-transistor hybrid inverters.
With the present interest in the use of variable frequency induction motors, state of the art inverters, whether they are thyristor or transistor based, are attracting attention. The thyristor inverter described in U.S. Pat. No. 3,207,974, which issued on Sept. 21, 1965, to W. McMurray, remains one of the most preferred, particularly in its modified form wherein a pair of diodes are connected across the commutation thyristors with a damping resistor connected between the juncture of the pair of diodes and the juncture of the commutation thyristors. This inverter is advantageous since it has a high efficiency, its commutation circuit components are small and it is suitable for pulse width modulation (PWM) operation. On the other hand, it has been found that this inverter has a propensity for misfirings and shoot-throughs and that protection against commutation failure or short circuit is difficult.
A further thyristor inverter is described in U.S. Pat. No. 4,344,123, which issued on Aug. 10, 1982, to P. Bhagwat and V. R. Stefanovic. It describes an efficient multilevel PWM inverter that utilizes a versatile commutation circuit. The commutation circuit is described in Canadian patent application No. 363,141 filed on Sept. 25, 1980, which corresponds to U.S. patent application Ser. No. 296,296, filed on Aug. 26, 1981, now U.S. Pat. No. 4,405,977 naming P. Bhagwat and V. R. Stefanovic as inventors. This commutation circuit has the unique feature of having zero charge on the commutation capacitor before and after a commutation, which offers tremendous flexibility in programming or in bypassing the commutations.
When the commutation circuits are designed for thyristor inverter motor drive applications, some safety margin must be allowed to successfully commutate an overload or fault current. Usually, commutation circuits are designed to commutate at least twice the full load current. In order to optimize the commutation circuit for minimum capacitance, the peak commutation circuit current will be I.sub.pk =1.5I, where I is the current to be commutated. As an example, for a motor with a peak full load current of 100 A, I.sub.pk =1.5(2.times.100)=300 A. The inverter should be able to take a step command from no load to full load and, therefore, regardless of the actual current to be commutated, a commutation circuit should always deliver an impulse current with the peak magnitude of I.sub.pk. In order to calculate the losses, both actual current which is commutated and the peak commutation circuit current are important.
Losses in a PWM thyristor inverter can be divided into fixed losses and variable losses. The fixed losses, which depend on the supply voltage rather than the actual value of the load current, consist of:
(a) I.sup.2 R losses in the commutation inductor and capacitor, and any other inductor in the path of the commutation current, PA1 (b) switching losses in the auxiliary SCR, and PA1 (c) losses in the snubber circuit across the auxiliary and main SCR. The losses which vary according to the load consist of: PA1 (a) losses in the di/dt inductor due to load current, PA1 (b) in the feedback diode during commutation and free wheeling period, PA1 (c) losses in the main SCR, and PA1 (d) trapped energy losses in the commutation and di/dt inductor. Since the fixed losses are high in a thyristor inverter irrespective of the actual current conduction of the switches, it is obvious that the efficiency of a thyristor inverter will be degraded when switching at low power levels. In PWM inverters operating at low frequencies, a majority of the commutations take place to commutate small magnitude currents resulting in a system which is inefficient.
Power transistor inverters have been designed particularly with the development of high power transistors, as small and medium power motor drives. However, these inverters do not satisfy the needs of high power applications.